1. Field of the Invention
The present invention relates to an operational amplifier circuit comprising a differential-amplification type amplifier circuit as a first stage and an amplifier circuit as a second stage.
2. Description of the Related Art
There has heretofore been known an operational amplifier (hereinafter abbreviated as "OP amp") circuit provided with a differential-amplification type amplifier circuit 41 as a first stage and an amplifier circuit 42 as a second stage as shown in FIG. 5 by way of example.
The amplifier circuit 41 has a pair of emitter-coupled input transistors 43, 44. The base of the input transistor 43 is used as a minus input IN- side and supplied with an input signal, whereas the base of the input transistor 44 is used as a plus input IN+ side and supplied with an input signal. The emitters of the input transistors 43, 44 are electrically connected to a power line 46 through a constant-current circuit 45. In addition, the collectors of the input transistors 43, 44 are electrically connected to the collectors of a pair of transistors 48, 49, respectively, which constitute a current mirror circuit 47. The emitters of the transistors 48, 49 are electrically connected to an earth or ground line 50.
On the other hand, the amplifier circuit 42 has a drive transistor 51 whose base is electrically connected between the collector of the input transistor 44 and the collector of the transistor 49. The collector of the drive transistor 51 is electrically coupled to the power line 46 through a resistor 52, whereas the emitter thereof is electrically connected to the ground line 50 via a resistor 53. In addition, the emitter of the drive transistor 51 is electrically coupled to the base of an output transistor 54. The collector of the output transistor 54 is electrically coupled to the power line 46 through a constant-current circuit 55, whereas the emitter thereof is electrically connected to the ground line 50.
Then, a phase-compensating capacitor 56 is electrically connected between the collector of the input transistor 44 serving as the output of the amplifier circuit 41 and the collector of the output transistor 54 serving as the output of the amplifier circuit 42. The phase-compensating capacitor 56 is provided to prevent the phase of an output signal of the amplifier circuit 42 from producing a 180.degree. phase shift or greater with respect to the phase of a signal input to the amplifier circuit 41.
Thus, when the input (minus input IN-) applied to the base of the input transistor 43 is higher in potential level than the input (plus input IN+) applied to the base of the input transistor 44 in the amplifier circuit 41, current flowing in a base junction (node) A of the drive transistor 51 through the input transistor 44 from the constant-current circuit 45 increases. As a result, the drive transistor 51 is turned on to bring the output transistor 54 into an on state, thereby causing the potential of the output signal OUT from the amplifier circuit 42 to drop toward ground or GND potential.
On the other hand, when the base input of the input transistor 43 is lower in potential level than that of the input transistor 44, current flowing into the transistor 48 through the input transistor 43 from the constant-current circuit 45 increases. Hence, the current is about to flow into the transistor 49 in the same manner as described above. As a result, the potential at the node A is reduced, and the drive transistor 51 is hence turned off to bring the output transistor 54 into an off state, thereby causing the potential of the output signal OUT from the amplifier circuit 42 to be raised toward a supply voltage VCC.
In this manner, the amplifier circuit 42 can produce a desired output signal OUT based on the minus input IN- and the plus input IN+ as the input signals applied to the amplifier circuit 41.
In the OP amp circuit referred to above, however, the potential at the node A is reduced to potential near the GND potential when the potential of the output signal OUT of the amplifier circuit 42 is saturated at the supply voltage VCC, i.e., reaches the saturation supply voltage VCC. Then, when the base input of the input transistor 48 is higher in potential level than the base input of the input transistor 44 and the potential of the output signal OUT from the amplifier circuit 42 is about to drop toward the GND potential, current, which is about to flow in the node A through the input transistor 44, flows into the phase-compensating capacitor 56, which is, in turn, charged by the current. Therefore, an increase in the potential at the node A is delayed only during a period in which the phase-compensating capacitor 56 is being charged, and the drive transistor 51 and the output transistor 54 are not turned on immediately. As a result, the output signal OUT of the amplifier circuit 42 still remains saturated at the supply voltage VCC, thereby causing a problem that a response delay occurs in a transition waveform of the output whose potential drops toward the GND potential.